1. Field of the Invention
The present invention relates to pipelined microprocessors and, more particularly, to a pipelined microprocessor that prevents the cache from being read when the contents of the cache are invalid.
2. Description of the Related Art
A pipelined microprocessor is a microprocessor that operates on instructions in stages so that, at each stage of the pipeline, a different function is performed on an instruction. As a result, multiple instructions move through the pipe at the same time much like to-be-assembled products move through a multistage assembly line.
FIG. 1 shows a block diagram that illustrates the flow of an instruction through a conventional pipelined processor. As shown in FIG. 1, the first stage in the pipe is a prefetch stage. In this stage, the to-be-executed instructions are retrieved from either an instruction cache or an external memory, and are then sequentially loaded into a prefetch buffer. The purpose of the prefetch stage is to fill the prefetch buffer so that one instruction can be advanced to the decode stage, the next stage in the pipe, with each clock cycle.
In the decode stage, each instruction moving through the pipe is decoded to determine what operation is to be performed. After the decode stage, an operand stage determines if data will be needed to perform the operation and, if needed, retrieves the data from memory. Following this, the operation specified by the instruction is performed in an execution stage, while the results of the operation are stored in a write-back stage.
In the ideal case, each instruction is advanced from one stage to the next with each successive clock cycle. Thus, while it takes five clock cycles for an instruction to propagate through the pipeline, the processor appears to complete the execution of each instruction in only one clock cycle.
One situation which can stall the pipeline, or prevent instructions from advancing from one stage to the next with each clock cycle, is the inability of the processor to obtain the instructions or data required by the processor within a single clock cycle. As a result, conventional pipelined processors typically utilize an on-chip cache memory to store a limited number of instructions and data values. Since the cache memory is on-chip, the cache can typically be accessed within a single clock cycle.
Although a cache provides a technique for accessing memory within a single clock cycle, cache memories consume a substantial amount of power each time the cache is accessed. Conventionally, this power consumption is minimized by only accessing the cache when a valid cache request is present. However, because the amount of power consumed by the cache during each access is large, there is a continuing need for other techniques that limit the power consumed by the cache.